1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to an output buffer for digital signals.
2. Description of the Related Art
As is known, in an integrated circuit, an output buffer for digital signals is an interface circuit which serves for driving a load which, in most cases, is outside the integrated circuit. Normally, the circuit is dimensioned on the basis of direct-current operating specifications, that is, on the basis of the maximum value of the supply voltage and on the maximum value of the current to be supplied to a predetermined resistive load. As a result of this dimensioning, the switching speed is often much greater than required and this may give rise to serious disadvantages. In particular, as the number of functions which can be integrated in a single chip of semiconductor material increases, the number of outputs of the integrated device increases. The outputs are often grouped in xe2x80x9cbusesxe2x80x9d and have to be switched simultaneously by the respective output buffers. In these cases, very high pulsed currents pass through the impedances and the parasitic resistances associated with the electrical connections between the integrated circuit and the external terminals during switching. These current transients require the external supply to deliver, for very short periods, currents much greater than those required on average for the operation of the device, and therefore necessitate the use of over-dimensioned supply means. This problem is experienced in particular when the integrated device forms part of portable apparatus, that is, of apparatus having limited electrical energy resources. Moreover, the current transients may give rise to spurious internal switching, and hence to losses or alterations of the data associated with the digital signal. In mixed integrated circuits, that is, those containing both digital portions and analog portions, the current transients may prejudice the performance of the analog circuits.
To prevent or at least attenuate the problems explained above, devices must be designed with supply-connection tracks of sufficiently large cross-section. A solution of this type is completely unsatisfactory since it leads to a great wastage of area and does not solve the problem of excessive demands on the supply.
A known output buffer designed to address the problems explained above is shown in FIG. 1. In this example, the buffer is constituted by four pairs of complementary MOS transistors connected so as to operate in phase opposition, in pairs (M1n-M4n; M1p-M4p), but it could be constituted by a much larger number of such pairs. The pairs of transistors are connected between two supply terminals, indicated by the earth symbol and +VDD, and have, as a common terminal, the drain electrodes of the transistors which are connected to an output terminal OUT. The gate electrodes of the first pair M1p, M1n are connected together to the input terminal IN of the buffer and the gate electrodes of the subsequent pairs are connected together to the gate electrodes of the respective preceding pairs by means of delay circuits which, in this example, have equal delay times xcex94t. The transistors are of a size such that each pair can supply one quarter of the output current to the load, not shown. As a result of the delays, a transition in the level of a signal applied to the input IN gives rise to a much slower transition in the output signal than in the input signal, reducing any current peaks. However, this circuit operates satisfactorily only if it is constituted by a large number of pairs of transistors. This involves the wastage of a large area of the integrated circuit so that this solution is not in practice very much favoured by designers.
Another known buffer is shown schematically in FIG. 2. It is formed by a single pair of complementary MOS transistors Mp and Mn controlled by respective driver stages DRp and DRn. The stages DRp and DRn operate in a manner such as to switch the respective transistors off rapidly and to switch them on slowly by the generation of a constant-current front long enough to cause the output OUT to switch gradually. However, this known buffer is rather complex and, in the same manner as the other known buffer described briefly above, supplies a current which varies in dependence on the load.
Aspects of the present invention involve an output buffer for digital signals in which the switching current, that is, the current delivered or absorbed during the transitions of the digital signal, is independent of the load. Aspects also include an output buffer for digital signals which is simple and reliable and occupies a small area.
Further to these and other aspects, an output buffer for digital signals has an output stage including a first output MOS transistor of a first type and a second MOS transistor of a second type with respective source electrodes connected to a first supply terminal and to a second supply terminal, respectively, drain electrodes connected together to an output terminal (OUT) of the buffer, and gate electrodes connected to an input terminal of the buffer by means of a first driver stage and a second driver stage, respectively.
The first driver stage includes a first circuit branch comprising first current-generator means connected between the gate electrode of the first output transistor and the second supply terminal and a first controlled electronic switch connected between the gate electrode of the first output transistor and the first supply terminal and having a control electrode connected to the input terminal of the buffer. The first driver further includes a second circuit branch comprising a first MOS transistor of the first type connected as a diode in series with a second controlled electronic switch between the gate electrode of the first output transistor and the first supply terminal, the second electronic switch having a control terminal connected to the output terminal of the buffer.
A second driver stage includes a third circuit branch comprising second current-generator means connected between the gate electrode of the second output transistor and the first supply terminal and a third controlled electronic switch connected between the gate electrode of the second output transistor and the second supply terminal (earth) and having a control electrode connected to the input terminal of the buffer. The second driver stage further includes a fourth circuit branch comprising a second MOS transistor of the second type connected as a diode in series with a fourth controlled electronic switch between the gate electrode of the second output transistor and the second supply terminal, the fourth electronic switch having a control terminal connected to the output terminal of the buffer.
Other features and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.